// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  ISR
// 12'h004  IFCR
// 12'h008  CCR1
// 12'h00C  CNDTR1
// 12'h010  CPAR1
// 12'h014  CMAR1
// 12'h01C  CCR2
// 12'h020  CNDTR2
// 12'h024  CPAR2
// 12'h028  CMAR2
// 12'h030  CCR3
// 12'h034  CNDTR3
// 12'h038  CPAR3
// 12'h03C  CMAR3
// 12'h044  CCR4
// 12'h048  CNDTR4
// 12'h04C  CPAR4
// 12'h050  CMAR4
// 12'h058  CCR5
// 12'h05C  CNDTR5
// 12'h060  CPAR5
// 12'h064  CMAR5
// 12'h06C  CCR6
// 12'h070  CNDTR6
// 12'h074  CPAR6
// 12'h078  CMAR6
// 12'h080  CCR7
// 12'h084  CNDTR7
// 12'h088  CPAR7
// 12'h08C  CMAR7
// -FHDR
// ---------------------------------------------------------------

module dma_regfile (
    input                  hclk                ,
    input                  hrstn               ,

    input                  hready              ,
    input  [31:0]          haddr               ,
    input                  hwrite              ,
    input  [01:0]          htrans              ,
    input  [02:0]          hsize               ,
    input  [31:0]          hwdataa              ,

//   output                 hreadyout           ,
//   output                 hreadyout_peri      ,
    input                   hsel_dma            ,
    output [31:0]           hrdata_dma
);

// ------------------------------------------------------------
// AHB write read enable
// ------------------------------------------------------------
wire            ahb_cs    = hsel_dma & hready & htrans[1];
wire            read_en   = ahb_cs & (~hwrite);
reg     [11:2]  addr;
reg             write_en;
reg     [31:0]  ff_rdata;

always @(posedge hclk or negedge hrstn) begin
    if (~hrstn) begin
        addr      <= 6'h0;
        write_en  <= 1'h0;
    end else begin
        addr      <= haddr[11:2];
        write_en  <= ahb_cs & (~hwrite);
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        hrdata_dma <= 32'b0;
    else if (read_en) 
        hrdata_dma <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------


// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------


always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
